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Table 1 Overview of HT countermeasures

From: Secure and Trustworthy Microelectronics: Vulnerabilities, Solutions, and Trends

Approaches

Reference

Detection/tolerance

Method

Weakness

Class of countermeasure

Software variant

TReC [25]

Runtime

Execution of multiple functionally equivalent software variants

Performance overhead and not applicable for all kind of HT models

Trojan tolerance

IC redundancy

SAFER PATH [26]

Runtime

Program execution in multiple processing elements

Performance and cost overhead with limited detection scope

Trojan tolerance

IP redundancy

TrojanGuard [27], HLS [28], task scheduling [43, 44]

Runtime

IP vendor diversity

Performance and cost overhead with limited detection scope

Trojan tolerance

Static analysis

ANGEL [45], COTD [46]

Pre-silicon

RTL code analysis using metrics line, statement, fsm, and toggle coverage etc.

Full coverage doesn’t guarantee HT-free design. Limited to designs combinational logic

Trojan detection

Formal methods

Proof check [15], verification [16]

Pre-silicon

Convert the design to proof checking format and checks security properties

Detection scope is limited and need sophisticated comprehensive properties

Trojan detection

IP monitoring

Many-core [47], ISA Power [48]

Runtime

Modification of hardware code to monitor execution

Performance and cost overhead with limited detection scope

Trojan detection

Side-channel

Power [17, 18], delay [19]

Post-silicon

Detecting anomalies in power consumption, electromagnetic emissions, and timing characteristics

Golden model required, sensitive to noise

Trojan detection

Logic testing

MERO [13], region based [14], Genetic Alg, FANCI, VeriTrust

Pre/post-silicon

Useful test-pattern generation and Boolean analysis to trigger rare logic conditions at internal nodes

Large HTs, test vector generation for large designs

Trojan detection

Design-for-Sec

Sensors [29, 49], OBISA [30], BISA [31]

Pre/post-silicon

On-chip trust evaluation modules for monitoring/detecting trojans in post-deployment stage

Performance and cost overhead with limited detection scope

Trojan detection/ prevention

Machine learning

Reverse engineering [34, 35], circuit feature analysis [36,37,38], side-channel analysis [39,40,41,42]

Pre/post-silicon

By utilizing different machine learning algorithms to use circuit features, i.e., structure, functionalities and parameters, the model tries to reveal the HTs or enhance the strategies

For rare and diverse trojan, it is challenging to build vast label data. Without golden reference, models struggle to generalize sophisticated HTs

Trojan detection

Graph matching

Similarity [32], CFG [33]

Pre/post-silicon

A library consists of HTs graph and search those in the graph of 3PIP using graph matching algorithms

Only work for known HTs graph

Trojan detection

Hardware obfuscation

Logic encryption [20, 50], HARPOON [21], camouflaging [22]

Pre-silicon

Increasing the complexity and obscuring the design and functionality

Increase complexity and design overhead with reliance on certain threat models

Trojan prevention

Split manufacturing

[23] 3D integration [24]

Pre-silicon

Cost and product deployment overhead

Dependency on external trust

Trojan prevention